1. Field of the Invention
This invention relates to a solid-state image pickup apparatus, a signal processing method for a solid-state image pickup apparatus, and an electronic apparatus.
2. Description of the Related Art
A solid-state image pickup apparatus is known which includes a unit pixel which in turn includes a photoelectric conversion section, a charge detection section and a transfer gate section for transferring charge accumulated in the photoelectric conversion section to the charge detection section. A solid-state image pickup apparatus of the type described usually carries out a noise removing process by correlation double sampling in order to remove noise upon a resetting operation. In the following description, the charge detection section is referred to as FD (Floating Diffusion) section. As a method of the noise removing process, a method which uses digital signal processing and another method which uses analog signal processing are available.
A solid-state image pickup apparatus which uses digital signal processing as a noise removing process is known and disclosed, for example, in Japanese Patent Laid-Open No. 2006-340044 (hereinafter referred to as Patent Document 1). The solid-state image pickup apparatus disclosed in Patent Document 1 incorporates column-parallel ADCs (Analog-Digital Converters; analog-digital conversion circuits) and is configured such that a plurality of unit pixels are arrayed in rows and columns and an ADC is disposed for each column.
In the solid-state image pickup apparatus incorporating column-parallel ADCs, a reset level Vrst read out first is set as a reference voltage Vzr for an AD conversion circuit, and the reference voltage Vzr is used to AD convert the reset level Vrst and a signal level Vsig. In particular, the reference voltage Vzr is made equal to the reset level Vrst so that, even if the reset level Vrst is fluctuated by noise, the output amplitude |Vsig−Vrst| of the pixel by signal charge can be included stably in an input voltage range of the AD conversion circuit.
Generally, the reference voltage Vzr of the AD conversion circuit can be adjusted only within a sufficiently small range with respect to the input voltage range of the AD conversion circuit. Accordingly, the reference voltage Vzr for the AD conversion circuit preferably is a signal whose fluctuation width is stable and limited like the reset level Vrst. On the contrary, a signal whose voltage exhibits a great amplitude in response to an incident light amount like the signal level Vsig is not suitable as the reference voltage Vzr for the AD conversion circuit.
A noise removing process of an existing solid-state image pickup apparatus is premised on an assumption that the reset level Vrst is read out first and the signal level Vsig is read out immediately succeeding the reset level Vrst as in the solid-state image pickup apparatus which incorporates column-parallel ADCs described above. On the other hand, a solid-state image pickup apparatus which cannot read out the reset level Vrst immediately preceding to the signal level Vsig cannot acquire, before the signal level Vsig of a certain unit pixel is AD converted, the reference voltage Vzr from the same pixel.
As a solid-state image pickup apparatus which cannot read out the reset level Vrst immediately preceding to the signal level Vsig, a complementary metal oxide semiconductor (CMOS) image sensor having a global exposure function is known and disclosed, for example, in Japanese Patent Laid-Open No. 2001-238132 (hereinafter referred hereinafter referred to as Patent Document 2). In the CMOS image sensor, in order to implement simultaneous exposure of all pixels, charge generated in the photoelectric conversion section is transferred to the FD section simultaneously with regard to all pixels. Then, in the state in which the signal charge is retained in the FD section, a reading out operation of the signal charge is carried out successively for all pixels.
As another solid-state image pickup apparatus which cannot read out the reset level Vrst immediately preceding to the signal level Vsig, another CMOS image sensor is known and disclosed in Japanese Patent Laid-Open No. 2009-020176 (hereinafter referred to as Patent Document 3). The solid-state image pickup apparatus disclosed in Patent Document 3 includes a memory section for retaining photocharge transferred thereto from the photoelectric conversion section separately from the charge detection section. Also a CMOS image sensor wherein photocharge generated by a PN junction is read out directly by an amplification transistor is known and disclosed, for example, in “128×128 CMOS PHOTODIODE-TYPE ACTIVE PIXEL, SENSOR WITH ON-CHIP TIMING CONTROL AND SIGNAL CHAINELECTRONICS,” SPIE, vol. 2415, Charge-Coupled Devices and Solid State Optical Sensors V, paper no. 34 (1995) (hereinafter referred to as Non-Patent Document 1). Further, an image sensor which uses an organic photoelectric conversion film is known and disclosed, for example, in Japanese Patent Laid-Open No. 2008-228265 (hereinafter referred to as Patent Document 4).
In a solid-state image pickup apparatus, the FD section is reset once upon simultaneous transfer from all pixels or upon starting of exposure, and therefore, at a timing at which a signal is to be read out, signal charge is accumulated or retained already in the FD section. Therefore, in order to remove fixed pattern noise such as a threshold value dispersion of an amplification transistor and so forth, it is necessary to set, after the signal level Vsig is read out, the FD section to a predetermined potential and read out the predetermined potential as the reset level Vrst as seen in FIG. 44.
However, in a solid-state image pickup apparatus wherein signal reading out is executed in a state in which signal charge is retained in the FD section for simultaneous exposure of all pixels or in a solid-state image pickup apparatus wherein signal charge is accumulated directly in the FD section and signal reading out is carried out, the FD section cannot be set to a predetermined potential immediate before the signal level Vsig is read out. In this instance, a reference voltage to be used for AD conversion of the signal level cannot be acquired. Therefore, a predetermined voltage is generated by external application or by means of a resistor array or the like and supplied as a reference voltage to the AD conversion circuit as disclosed, for example, in Japanese Patent Laid-Open No. 2006-020176 (hereinafter referred to as Patent Document 5).